• Corpus ID: 9886482

A single-instance incremental SAT formulation of proof- and counterexample-based abstraction

@article{En2010ASI,
  title={A single-instance incremental SAT formulation of proof- and counterexample-based abstraction},
  author={Niklas E{\'e}n and Alan Mishchenko and Nina Amla},
  journal={Formal Methods in Computer Aided Design},
  year={2010},
  pages={181-188}
}
This paper presents an efficient, combined formulation of two widely used abstraction methods for bit-level verification: counterexample-based abstraction (CBA) and proof-based abstraction (PBA). Unlike previous work, this new method is formulated as a single, incremental SAT-problem, interleaving CBA and PBA to develop the abstraction in a bottom-up fashion. It is argued that the new method is simpler conceptually and implementation-wise than previous approaches. As an added bonus, proof… 

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References

SHOWING 1-10 OF 19 REFERENCES

Iterative abstraction using SAT-based BMC with proof analysis

TLDR
This work uses the proof analysis technique with SAT-based BMC, in order to generate useful abstract models that can be used to obtain proofs of correctness, or to perform deeper searches for counterexamples.

Combining Abstraction Refinement and SAT-Based Model Checking

TLDR
It is concluded that when using interpolation-based model checking, measures must be taken to prevent the overhead of abstraction refinement from dominating runtime.

A Hybrid of Counterexample-Based and Proof-Based Abstraction

TLDR
In a study of a large number of industrial verification problems, it is found that there is a strong relation between the effort applied in the refinement phase and the number of refinement iterations, and proof-based abstraction is substantially more efficient than counterexample- based abstraction.

Automatic Abstraction without Counterexamples

A method of automatic abstraction is presented that uses proofs of unsatisfiability derived from SAT-based bounded model checking as a guide to choosing an abstraction for unbounded model checking.

Efficient Abstraction Refinement in Interpolation-Based Unbounded Model Checking

TLDR
It is shown that for passing properties abstraction refinement leads to proofs that often require examination of shorter paths, and the techniques developed to minimize such overhead to the point that even for failing properties the abstraction refinement scheme remains competitive.

Interpolation and SAT-Based Model Checking

TLDR
In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Applying Logic Synthesis for Speeding Up SAT

TLDR
This paper explores preprocessing of circuit-based SAT problems using recent advances in logic synthesis using DAG-aware logic minimization and a novel type of structural technology mapping, which reduces the size of the CNF derived from the circuit.

Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis

TLDR
A SAT based automatic abstraction refinement framework for model checking systems with several thousand state variables in the cone of influence of the specification and a computationally more advantageous approach in which the abstract transition relation is approximated by pre-quantifying invisible variables during image computation.

Formal property verification by abstraction refinement with formal, simulation and hybrid engines

  • Dong WangPei-Hsin Ho R. Damiano
  • Computer Science
    Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
  • 2001
TLDR
RFN, a formal property verification tool based on abstraction refinement, is developed to verify various properties of real-world RTL designs containing approximately 5,000 registers, which represents an order of magnitude improvement over previous results.

Efficient Circuit to CNF Conversion

TLDR
This work outlines a simple and expressive data structure for describing arbitrary circuits, as well as an algorithm for converting circuits to CNF, and shows that the CNF problems it generates are consistently smaller and more quickly solved by modern SAT solvers than the C NF problems generated by current CNF generation methods.