A single-chip receiver for multi-user low-noise block down-converters

@article{Copani2005ASR,
  title={A single-chip receiver for multi-user low-noise block down-converters},
  author={Tino Copani and S. A. Smerzi and Giovanni Girlando and G. Ferla and Giuseppe Palmisano},
  journal={ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.},
  year={2005},
  pages={438-608 Vol. 1}
}
A 12GHz single-chip receiver for multi-user low-noise block down-converters is presented. The 3.3mm/spl times/2mm die is implemented in a 50GHz-f/sub T/ 0.8 /spl mu/m silicon bipolar technology and includes two down-converter channels and a 10.2GHz local oscillator synthesizer. The receiver features a 7.8dB SSB NF, an output P/sub 1dB/ of 5dBm with 32dB conversion gain and phase noise of -96dBc/Hz at 100kHz offset from the 10.2GHz carrier. 

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A 12GHz silicon bipolar receiver for digital satellite applications

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) • 2004

ASTRA Reception Equipment Recommendations for DTH and SMATV Systems

ASTRA
Technical Recommendations, June, 2002. • 2002
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