A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

@article{Zargari2004ASD,
  title={A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN},
  author={Masoud Zargari and M. Terrovitis and S. Jen and B. Kaczynski and MeeLan Lee and M. Mack and S. Mehta and Sunetra Mendis and Keith Onodera and Hirad Samavati and W. Si and Kamaljit Singh and Ali Tabatabaei and David Ollier Weber and D. Su and B. Wooley},
  journal={IEEE Journal of Solid-State Circuits},
  year={2004},
  volume={39},
  pages={2239-2249}
}
A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are… CONTINUE READING
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