A self-repairing multiplexer-based FPGA inspired by biological processes

@inproceedings{Tempesti1998ASM,
  title={A self-repairing multiplexer-based FPGA inspired by biological processes},
  author={Gianluca Tempesti},
  year={1998}
}
These Ecole polytechnique federale de Lausanne EPFL, n° 1827 (1998)Groupe TempestiLaboratoire de systemes logiques Reference doi:10.5075/epfl-thesis-1827Print copy in library catalog Record created on 2005-03-16, modified on 2016-08-08 

Self-repairing embryonic memory arrays

TLDR
This work investigates the causes and influences of soft fails over the current Embryonics framework and proposes a solution for the identified vulnerability based on error correcting codes, and provides a reliability comparison between memory structures with and withouterror correcting codes.

An embryonic approach to reliable digital instrumentation based on evolvable hardware

TLDR
This paper presents a technique based on reconfigurable hardware coupled with a novel backpropagation algorithm for reconfiguration, together referred to as evolvable hardware (EHW), for ensuring reliability in digital instrumentation.

Efficient self-replication of digital circuits in programmable logic devices

TLDR
This work shows how the Tom Thumb self-replication algorithm can be extended to take into account realistic FPGA architectures and representative processor-scale digital logic circuits.

Self-replication for reliability: bio-inspired hardware and the embryonics project

TLDR
This paper provides an overview of the latest research in the domain of the self-replication of processing elements within a programmable logic substrate, a key prerequisite for achieving system-level fault tolerance in the bio-inspired approach.

Modeling of Bio-Inspired Self-Repairing Digital System

TLDR
The system inspired by endocrine cellular communication, that simplifies the rerouting process and is efficient enough for application with real fault-tolerant systems dealing with harsh and remote environments, such as outer space or deep.

Self-replicating hardware for reliability: The embryonics project

TLDR
An overview of the latest research in the domain of the self-replication of processing elements within a programmable logic substrate, a key prerequisite for achieving system-level fault tolerance in the Embryonics project's bio-inspired approach.

Biology Meets Electronics: The Path to a Bio-inspired FPGA

TLDR
Some of the peculiar features of the FPGA the authors designed to efficiently implement their embryonic machines are described, and the issues of memory storage and of self-repair are discussed, critical concerns for the implementation of their bio-inspired machines.

Embryonics: Artificial Cells Driven by Artificial DNA

TLDR
MuxTree, a new coarse-grained FPGA, is designed to implement embryonic machines, to address the issues posed by the memory storage and the advances made to achieve more robust memory structures.

Reliability assessment in embryonics inspired by fault-tolerant quantum computation

TLDR
A complete and original approach to the reliability analysis for Embryonics is proposed, by adopting the accuracy threshold measure, taken from fault-tolerant quantum computing theory, as the main parameter for the qualitative evaluation.

The Embryonics Project: Specifications of the Muxtree Fields Programmable Gate Array

TLDR
This document is intended as a summary of the final specifications of MUXTREE® necessary to be able to effectively use the molecules as a programmable circuit.
...

References

SHOWING 1-10 OF 143 REFERENCES

Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays

TLDR
Fault Tolerance Through Reconfiguration in VLSI and "I Arrays" is included in the Computer Systems series, edited by Herb Schwetman and presents the authors' own results in the reconfiguration of processing arrays.

Field-programmable gate arrays

TLDR
FPGAs enable engineers to mitigate the effects entailed by the wellknown tradeoff in computing between cost and performance, and combine the advantages of both general-purpose processors and specialized circuits.

Logic design principles - with emphasis on testable semicustom circuits

  • E. McCluskey
  • Art
    Prentice Hall series in computer engineering
  • 1986
TLDR
Logic design principles: with emphasis on testable semicustom circuits, Logic design principles with focus on testability semicustomcircuits, and more.

Digital systems testing and testable design

TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.

Highly parallel computing

Part 1 Foundations: overview - overview and scope of this book, definition and driving forces, questions raised, emerging answers, previous attempts why success now?, conclusions and future

Digital Hardware Testing: Transistor-Level Fault Modeling and Testing

TLDR
Digital Hardware Testing presents realistic transistor-level fault models and testing methods for all types of circuits, with coverage of boundary scan and emerging technologies such as partial scan, cross check, and circular self-test-path.

Towards Evolvable Hardware

TLDR
From the combination of knowledge and actions, someone can improve their skill and ability, which will lead them to live and work much better and this towards evolvable hardware tells you.

Digital circuit testing and testability

  • P. Lala
  • Computer Science, Engineering
  • 1997
TLDR
Test Generation for Combinational Logic Circuits: Fault Diagnosis of Digital Circuits and Testing of Sequential Circuits as IterativeCombinational Circuits.

Testing and Reliable Design of CMOS Circuits

TLDR
This paper focuses on the development of Robust Testability in Static and Dynamic CMOS Circuits, and on the design of these Circuits using the Chiang-Vranesic method.
...