A second-order semi-digital clock recovery circuit based on injection locking

  title={A second-order semi-digital clock recovery circuit based on injection locking},
  author={M.-J.E. Lee and W. Dally and J. Poulton and Tracy Greer and J. Edmondson and Ramin Farjad-Rad and Hiok-Tiaq Ng and Rohit Rathi and Ramesh Senthinathan},
  journal={2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.},
  pages={74-75 vol.1}
A 3.125Gb/s clock recovery circuit in 0.18/spl mu/m CMOS comprises a multiplying delay-locked loop (MDLL), an injection-locked slave oscillator and a phase control unit. Injection locking reduces MDLL clock distortion and varies the delay of the recovered clock, while a frequency loop in the phase control unit ameliorates the trade off between phase wander and frequency tolerance. Experimental results show high frequency jitter tolerance is improved by 0.08UI. 
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A 2Gb/s/pin Asymmetric Serial Link

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