A scheduling model for reduced CPU energy

  title={A scheduling model for reduced CPU energy},
  author={F. Frances Yao and Alan J. Demers and Scott Shenker},
  journal={Proceedings of IEEE 36th Annual Foundations of Computer Science},
The energy usage of computer systems is becoming an important consideration, especially for battery-operated systems. [] Key Method In this model, each job is to be executed between its arrival time and deadline by a single processor with variable speed, under the assumption that energy usage per unit time, P, is a convex function, of the processor speed s. We give an off-line algorithm that computes, for any set of jobs, a minimum-energy schedule.

Figures from this paper

Flow Time Minimization under Energy Constraints
This paper targets a scheduling problem on a processor with the capability of dynamic voltage scaling (DVS), which could reduce the power consumption by slowing down the processor speed.
A Linear Time Algorithm for Computing Off-line Speed Schedules Minimizing Energy Consumption
This work proposes a linear time algorithm that checks the schedulability of the given set of n jobs and computes an optimal speed schedule, based on a completely different idea: instead of computing the critical intervals, it sweeps the set of jobs and uses a dynamic programming approach to compute an optimalspeed schedule.
Discrete and continuous min-energy schedules for variable voltage processors
This work gives an algorithm with running time O(n(2) log n) for finding the min-energy schedule based on finding successive approximations to the optimal schedule by an efficient partitioning of the job set into high and low speed subsets by any speed threshold, without computing the exact speed function.
Energy Efficient Deadline Scheduling in Two Processor Systems
A new analysis of the energy usage of the speed function OA with respect to the optimal two-processor schedule and a new online strategy for selecting jobs for the two processors.
Using resource reservation techniques for power-aware scheduling
The GRUB-PA algorithm is presented, a new scheduling algorithm for power-aware systems that can efficiently handle systems consisting of hard and soft real-time tasks and is implemented in the Linux OS.
Algorithms for power savings
This paper examines two different mechanisms for saving power in battery-operated embedded systems and gives an off line algorithm which is within a factor of three of the optimal algorithm and an online algorithm with a constant competitive ratio.
A Heuristic-Based Approach for Reducing the Power Consumption of Real-Time Embedded Systems
  • V. Radulescu, S. Andrei, A. Cheng
  • Computer Science
    2014 16th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing
  • 2014
This paper presents an approach on improving the energy consumption of a real-time system by reducing the CPU frequency whenever possible, without breaking the task deadlines.
On Energy-Optimal Off-Line Scheduling for Fixed-Priority Hard Real-Time Systems On a Variable Speed Processor
This paper proves that the problem of energy-optimal off-line voltage scheduling for fixed-priority hard real-time systems is NP-hard, and presents a fully polynomial time approximation scheme (FPTAS) for the problem.
Energy-Centric Scheduling for Real-Time Systems
Several scheduling approaches for low energy are described in the thesis, most targeting variable speed processor architectures, and an energy-efficient extension of the earliest deadline first priority assignment policy is proposed, aimed at tasks with probabilistic execution time.
A Linear Time Algorithm Computing the Optimal Speeds Minimizing Energy Under Real-Time Constraints
We consider the classical problem of minimizing off-line the total energy consumption required to execute a set of n real-time jobs on a single processor with varying speed. Each real-time job is


Scheduling for reduced CPU energy
A new metric for cpu energy performance, millions-of-instructions-per-joule (MIPJ), and several methods for varying the clock speed dynamically under control of the operating system, and examine the performance of these methods against workstation traces.
Comparing algorithm for dynamic speed-setting of a low-power CPU
This work clarifies a fundamental power vs. delay tradeoff, as well as the role of prediction and of smoothing in dynamic speed-setting policies, and concludes that success seemingly depends more on simple smoothing algorithms than on sophisticated prediction techniques.
Low-power CMOS digital design
An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
An energy-efficient CMOS line driver using adiabatic switching
The authors describe the adiabatic charging principle used, which allows a digital circuit designer to directly trade off switching time for increased energy efficiency.
Compar - ing algorithms for dynamic speed - setting of a low - power CPU . preprint
  • Self - clocked structures for low power systems . Computer Systems Laboratory , Stanford University , ARPA semi - annual report , December
  • 1934
Self-clocked structures for low power systems
  • ARPA semi-annual report
  • 1993
Comparing algorithms for dynamic speed-setting of a lowpower CPU
  • Comparing algorithms for dynamic speed-setting of a lowpower CPU
Low-power CMOS digital design. JSSC
  • 1992