A scalable model based RTL framework zamiaCAD for static analysis

@article{Tsepurov2012ASM,
  title={A scalable model based RTL framework zamiaCAD for static analysis},
  author={Anton Tsepurov and Gunter Bartsch and Rainer Dorsch and Maksim Jenihhin and Jaan Raik and Valentin Tihhomirov},
  journal={2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)},
  year={2012},
  pages={171-176}
}
As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous size, and thus, to scale well. This paper presents an open-source framework zamiaCAD based on a scalable model that includes both, a comprehensive elaboration front-end for RTL design and design processing back-end flows. The persistence and scalability are guaranteed by a custom-designed and highly optimized object database. As an HDL… CONTINUE READING
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References

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Showing 1-6 of 6 references

Ghdl

  • T. Gingold
  • A V HDL compiler
  • 2012
1 Excerpt

Rt-Ievel itc 99 benchmarks and first atpg results

  • F. Como, M. S. Reorda, G. Squillero
  • pages 44-53
  • 2000
1 Excerpt

and T

  • E. M. Clarke, M. Fujita, S. P. Rajan, T. Reps, S. Shankar
  • Teitel­ baum. Program slicing of hardware…
  • 1999
1 Excerpt

Digital system design automation: lan­ guages

  • M. Breuer, M. MacDougall
  • simulation & data base. Digital system design…
  • 1975
1 Excerpt

Booledozer : Logic synthesis far asics

  • H. H. Chao, P. J. Osler
  • IBM Journal of Research and Development

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