A routing algorithm for flip-chip design

@article{Fang2005ARA,
  title={A routing algorithm for flip-chip design},
  author={Jia-Wei Fang and I-Jye Lin and Ping-Hung Yuh and Yao-Wen Chang and Jyh-Herng Wang},
  journal={ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.},
  year={2005},
  pages={753-758}
}
The flip-chip package gives the highest chip density of any packaging method to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs. In this paper, we propose the first router for the flip-chip package in the literature. The router can redistribute nets from wire-bonding pads to bump pads and then route each of them. The router adopts a two-stage technique of global routing followed by detailed routing. In global routing, we use the network flow algorithm to solve the… CONTINUE READING

Similar Papers

Figures, Tables, Results, and Topics from this paper.

Key Quantitative Results

  • Experimental results based on seven real designs from the industry demonstrate that the router can reduce the total wirelength by 10.2%, the critical wirelength by 13.4%, and the signal skews by 13.9%, compared with a heuristic algorithm currently used in industry.
  • Experimental results based on seven real designs from the industry demonstrate that the router can reduce the total wirelength by 10.2%, the critical wirelength by 13.4%, and the signal skews by 13.9%, compared with a heuristic algorithm currently used in industry.
  • By formulating the assignment as a maximum .ow problem and applying the minimum-cost maximum-.ow algorithm, we can guarantee 100% detailed routing completion after the assignment.
  • In addition to the traditional single-layer routing with only routability optimization, our RDL router also tries to optimize the total wirelength and the signal skews between a pair of signal nets under the 100% routing completion constraint. Experimental results based on seven real designs from the industry demonstrate that the router can reduce the total wirelength by 10.2%, the critical wirelength by 13.4%, and the signal skews by 13.9%, compared with a heuristic algorithm currently used in industry.

Citations

Publications citing this paper.
SHOWING 1-10 OF 28 CITATIONS

An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design

  • 2007 44th ACM/IEEE Design Automation Conference
  • 2007
VIEW 16 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

Area-I/O RDL routing for chip-package codesign considering regional assignment

  • 2010 IEEE Electrical Design of Advanced Package & Systems Symposium
  • 2010
VIEW 4 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

Recent research development in flip-chip routing

  • 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
  • 2010
VIEW 5 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

Flip-chip routing with IO planning considering practical pad assignment constraints

  • 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
  • 2018
VIEW 2 EXCERPTS
CITES METHODS & BACKGROUND

Scalable, high-quality, SAT-based multi-layer escape routing

  • 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
  • 2016
VIEW 2 EXCERPTS
CITES BACKGROUND

Ordered escape routing using network flow and optimization model

  • 2015 6th International Conference on Automation, Robotics and Applications (ICARA)
  • 2015

A sorting-based IO connection assignment for flip-chip designs

  • 2013 IEEE 10th International Conference on ASIC
  • 2013
VIEW 1 EXCERPT
CITES METHODS

Advances in PCB Routing

W D.F.
  • 2012
VIEW 1 EXCERPT

Correctly Modeling the Diagonal Capacity in Escape Routing

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2012

On effective flip-chip routing via pseudo single redistribution layer

  • 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)
  • 2012
VIEW 1 EXCERPT
CITES METHODS