A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS

@article{Ioannou2011ARR,
  title={A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS},
  author={D. Ioannou and Kai Zhao and Aditya Bansal and B. P. Linder and Ronald J. Bolam and E. Cartier and J.-J. Kim and Rahul M. Rao and Giuseppe La Rosa and G E Massey and Michael Hauser and K. Das and J. H. Stathis and Julia Aitken and Dinesh Badami and Steven W. Mittl},
  journal={2011 International Reliability Physics Symposium},
  year={2011},
  pages={CR.1.1-CR.1.4}
}
A robust reliability characterization / modeling approach for accurately predicting Bias Temperature Instability (BTI) induced circuit performance degradation in High-k Metal Gate (HKMG) CMOS is presented. A series of device level stress experiments employing both AC and DC stress/relax BTI measurements are undertaken to characterize FET's threshold voltage instability response to a dynamic (inverter type) operation. Results from the AC stress experiments demonstrate that VT instability is… CONTINUE READING
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