A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability

@article{Kong2018ARS,
  title={A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability},
  author={Debin Kong and Jia Yuan and Shan-shan Li and Heng You and Shushan Qiao},
  journal={IEICE Electron. Express},
  year={2018},
  volume={15},
  pages={20180758}
}

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