A resource-efficient probabilistic fault simulator

@article{May2013ARP,
  title={A resource-efficient probabilistic fault simulator},
  author={David May and Walter Stechele},
  journal={2013 23rd International Conference on Field programmable Logic and Applications},
  year={2013},
  pages={1-4}
}
The reduction of CMOS structures into the nanometer regime, as well as the high demand for low-power applications, animating to further reduce the supply voltages towards the threshold, results in an increased susceptibility of integrated circuits to soft errors. Hence, circuit reliability has become a major concern in today's VLSI design process. A new approach to further support these trends is to relax the reliability requirements of a circuit, while ensuring that the functionality of the… CONTINUE READING

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