A resilience roadmap

  title={A resilience roadmap},
  author={Sani R. Nassif and Nikil Mehta and Yu Cao},
  journal={2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)},
Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults. This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going… CONTINUE READING
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