A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators

@article{Jiang2010ARJ,
  title={A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators},
  author={Yang Jiang and Kim-Fai Wong and Chen-Yan Cai and Sai-Weng Sin and U Seng-Pan and Rui Paulo Martins},
  journal={2010 IEEE Asia Pacific Conference on Circuits and Systems},
  year={2010},
  pages={1011-1014}
}
A clock generation technique for reducing the clock-jitter sensitivity of Switched current (SI) Return-to-Zero (RZ) DAC in CT ΣΔ modulators is presented in this paper. While realizing the clock-jitter insensitivity, this technique ensures that the feedback period can be utilized more efficiently so that the amplitude of feedback current can be reduced. The proposed technique employs simple digital elements to generate a fixed-pulse-width feedback control clock. It was verified in a 2nd order, 1… CONTINUE READING