A recursive fast multiplier

@article{Danysh1998ARF,
  title={A recursive fast multiplier},
  author={A. N. Danysh and E. E. Swartzlander},
  journal={Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)},
  year={1998},
  volume={1},
  pages={197-201 vol.1}
}
This paper presents a recursive fast multiplication algorithm. The paper defines the algorithm and applies it to two's complement signed multiplication. A step-by-step approach is given that discusses the architectural and logic implementation in detail. A random, self-checking, simulation program verifies the correctness of the recursive multiplication algorithm. The paper analyzes the speed and gate count of the design and compares the results to other multiplier designs. 
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References

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C S. Wallace
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