A reconfigurable channel codec coprocessor for software radio multimedia applications


This paper describes a coprocessor architecture for channel coding and decoding in software radio high bit rate applications. The proposed approach has been implemented in VDHL code: After a brief introduction about main target applications, and the motivation for the proposed architecture, we show the high level device layout, dwelling upon every single… (More)
DOI: 10.1109/ISCAS.2003.1205881


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