A reconfigurable 8 GOP ASIC architecture for high-speed data communications

Abstract

A flexible and reconfigurable signal processing ASIC architecture has been developed, simulated, and synthesized. The proposed architecture compares favorably to classical DSP and FPGA solutions. It differs from general-purpose reconfigurable computing (RC) platforms by emphasizing high-speed application-specific computations over general-purpose… (More)
DOI: 10.1109/49.895021

Topics

17 Figures and Tables

Cite this paper

@article{Grayver2000AR8, title={A reconfigurable 8 GOP ASIC architecture for high-speed data communications}, author={Eugene Grayver and Babak Daneshrad}, journal={IEEE Journal on Selected Areas in Communications}, year={2000}, volume={18}, pages={2161-2171} }