A read-monitored write circuit for 1T1M multi-level memristor memories

@article{Manem2011ARW,
  title={A read-monitored write circuit for 1T1M multi-level memristor memories},
  author={Harika Manem and Garrett S. Rose},
  journal={2011 IEEE International Symposium of Circuits and Systems (ISCAS)},
  year={2011},
  pages={2938-2941}
}
Technology migration into nano and molecular scales has led to the design of several hybrid CMOS/nano logic and memory architectures that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale memory and logic systems by facilitating the implementation of multi-level logic. In this work we propose a sneak-path free memory architecture, the 1T1M (1 transistor per memristor) that provides for 2-bit… CONTINUE READING
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