A rated-clock test method for path delay faults

@article{Bose1998ART,
  title={A rated-clock test method for path delay faults},
  author={Soumitra Bose and Prathima Agrawal and Vishwani D. Agrawal},
  journal={IEEE Trans. VLSI Syst.},
  year={1998},
  volume={6},
  pages={323-331}
}
Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test… CONTINUE READING