A proposed 10-T full adder cell for low power consumption


This paper presents an improved circuit design of low power 1-bit full adder circuit. The circuit is designed and implemented based on top-down approach using total number of 10 transistors, thereby, known as 10-T cell. After simulation of the circuit, a clear view of the circuit performance, in terms of power, delay, area was studied. The performance of… (More)


5 Figures and Tables

Slides referencing similar topics