A priority-expression-based burst scheduling of memory reordering access

Abstract

The performance of modern computer system is greatly limited by the bandwidth of DRAM-based memory. Altering the sequence of main memory accesses can reduce observed access latency, therefore improve bus utilization. While previous reordering mechanisms consider factors related to memory access separately, this paper groups several factors together to build… (More)
DOI: 10.1109/ICSAMOS.2008.4664865

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