A pr 2 01 5 The Influence of Malloc Placement on TSX Hardware Transactional Memory

@inproceedings{Dice2015AP2,
  title={A pr 2 01 5 The Influence of Malloc Placement on TSX Hardware Transactional Memory},
  author={Dave Dice},
  year={2015}
}
  • Dave Dice
  • Published 2015
The hardware transactional memory (HTM) implementation in Intel’s i7-4770 “Haswell” processor [14, 15] tracks the trans ctional read-set in the L1 (level-1), L2 (level-2) and L3 (level-3) c aches and the write-set in the L1 cache. Displacement or eviction o f readset entries from the cache hierarchy or write-set entries fr om the L1 results in abort. We… CONTINUE READING