A power-optimal repeater insertion methodology for global interconnects in nanometer designs

@article{Banerjee2002APR,
  title={A power-optimal repeater insertion methodology for global interconnects in nanometer designs},
  author={Kaustav Banerjee and Amit Mehrotra},
  journal={IEEE Transactions on Electron Devices},
  year={2002},
  volume={49},
  pages={2001-2007}
}
This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power… Expand

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