A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing

@article{Murachi2008APS,
  title={A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing},
  author={Yuichiro Murachi and Tetsuya Kamino and Junichi Miyakoshi and Hiroshi Kawaguchi and Masahiko Yoshimoto},
  journal={2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)},
  year={2008},
  pages={63-66}
}
This paper describes a unique SRAM architecture for super- parallel video processing. It features one cycle functional access of a rectangular image data (n x m pixels) with segmentation-free. To achieve this accessibility, a local word-line select scheme and a merged X-decoder method are newly introduced with elimination of extra X-decoder employed in usage of the conventional divided SRAM macro. The proposed SRAM has been adopted to a search window buffer for H.264 motion estimation processor… CONTINUE READING

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