A polyphase architecture for serial-input convolvers

@article{Dadda1990APA,
  title={A polyphase architecture for serial-input convolvers},
  author={Luigi Dadda},
  journal={VLSI Signal Processing},
  year={1990},
  volume={2},
  pages={17-27}
}
It is shown that a cascade of carry-free serial-parallel multipliers, fed by bit-serial samples with no separation between successive samples (i.e., with maximum sampling rate for a given bit rate), produces one convolution value every p with p > 1. This circuit is called a phase-convolver, and it is shown that a full convolver can be obtained by associating p phase convolvers (polyphase convolver). Under some assumptions, a polyphase convolver can be implemented as a stack of bit-slices. It… CONTINUE READING

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Showing 1-9 of 9 references

Serial-Input Serial-Output Bit Sliced Convolver," Proc

  • L. Dadda, L. Breveglieri
  • ICCD '88,
  • 1988
Highly Influential
4 Excerpts

L

  • L. Breveglieri
  • Dadda, and D. Sciuto, "Testing of Serial-Input…
  • 1989
1 Excerpt

Use of BiDirectional Data Flow in Bit-Level Systolic Array Chips" Electronic Letters, Vol

  • J. V. McCanny, R. A. Evans, J. G. McWhirter
  • 22,
  • 1986
1 Excerpt

Danielsson , " Serial - Parallel Convolvers , " IEEE Trans

  • J. G. McWhirter McCanny, K. Wood
  • 1984

Optimized Bit Level Systolic Array for Convolution "

  • J. G. McWhirter
  • lEE Proc . E Commun . Radar & Signal Processing
  • 1984

Optimized Bit Level Systolic Array for Convolution" lEE Proc

  • J. V. McCanny, J. G. McWhirter, K. Wood
  • E Commun. Radar & Signal Processing, Vol. 131…
  • 1984
1 Excerpt

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