A pattern matching algorithm for verification and analysis of very large IC layouts


We propose a simple, isometry invariant pattern matching algorithm for an effective data reduction useful in layout-related data processing of very complex IC designs. The repeatable geometrical features and attributes are stored in a pattern database. Original pattern instance, or its geometrical attributes, may be quickly regenerated based both on the… (More)
DOI: 10.1145/274535.274554


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