A pattern compaction technique for power estimation based on power sensitivity information

@article{Hsu2001APC,
  title={A pattern compaction technique for power estimation based on power sensitivity information},
  author={Chih-Yang Hsu and Chaur-Wen Wei and Wen-Zen Shen},
  journal={ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)},
  year={2001},
  volume={5},
  pages={467-470 vol. 5}
}
We propose an efficient power estimation technique for CMOS combinational circuits based on power sensitivity information of primary inputs. We compacted a large sequence of input patterns into a much smaller ones, which also preserved the statistical properties of the original sequence. The experimental results showed our compaction method achieved high compaction ratio within reasonable loss in the accuracy for average power estimation. 

Figures and Topics from this paper.

References

Publications referenced by this paper.
SHOWING 1-8 OF 8 REFERENCES

Hierarchical Sequence Compaction lor Power Estimation

  • DAC
  • 1997

Poncho. "Fast Power Estimation for Deterministic Input Streams

  • ICCAD
  • 1997

Sensitivit> of PoLver' Dissipation to Uncertainties in Primarb

Z. Chen. K. Raj.. T.L. Chou
  • Input Specitication". in ICCAD
  • 1997

'A Novel Methodolog)

S. Y. Huang. K.T. Cheng. K. c'. Chen. Mike T.C. Lee
  • for Transistor-Level Power Estimation'.. i n ISLPED
  • 1996

*Improving the efticienc? of p o w x simulators by input vector compaction

  • 1996

I.White. "Estimation of po\ver dissipation

SJstenis. Ma
  • 1989