A partitioning approach to design fault-tolerant arithmetic arrays

  title={A partitioning approach to design fault-tolerant arithmetic arrays},
  author={Thou-Ho Chen and Liang-Gee Chen and Yeu-Shen Jehng},
  journal={Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]},
An alternative fault-tolerant design in VLSI-based arithmetic arrays using the partitioning technique is presented. The basic concept is that the arithmetic array can be divided into m parts and its operation can be completed through m iterative calculations with some one part. By taking three such parts with a majority-voting technique at each iteration, error correction can be achieved through m-step computations. This leads to the same fault tolerance capability as triple modular redundancy… CONTINUE READING


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Publications referenced by this paper.
Showing 1-5 of 5 references


D. K. Pradhan, Fault-tolerant computing theorey, +3 authors NI Englewood Cliffs
B. W. Johnson, Design and analysis of fault tolerant digital systems. Addison-Wesley. • 1989

Fault and error models for VLSI

Proceedings of the IEEE • 1986
View 1 Excerpt

Principles of CMOS VLSI design

N. Weste, K. Eshraghian
Addison-Wesley • 1985
View 1 Excerpt

Computer arithmetic: principles

K. Hwang

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