A partitioning approach to design fault-tolerant arithmetic arrays

@article{Chen1992APA,
  title={A partitioning approach to design fault-tolerant arithmetic arrays},
  author={Thou-Ho Chen and Liang-Gee Chen and Yeu-Shen Jehng},
  journal={Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]},
  year={1992},
  pages={432-439}
}
An alternative fault-tolerant design in VLSI-based arithmetic arrays using the partitioning technique is presented. The basic concept is that the arithmetic array can be divided into m parts and its operation can be completed through m iterative calculations with some one part. By taking three such parts with a majority-voting technique at each iteration, error correction can be achieved through m-step computations. This leads to the same fault tolerance capability as triple modular redundancy… CONTINUE READING

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