A parallel LSI architecture for LDPC decoder improving message-passing schedule

@article{Shimizu2006APL,
  title={A parallel LSI architecture for LDPC decoder improving message-passing schedule},
  author={Kazunori Shimizu and Tatsuyuki Ishikawa and Nozomu Togawa and Takeshi Ikenaga and Satoshi Goto},
  journal={2006 IEEE International Symposium on Circuits and Systems},
  year={2006},
  pages={4 pp.-}
}
This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) the column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently; and (ii) the proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These… CONTINUE READING
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Cavallaro , " Semi - Parallel Reconfigurable words as that based on the schedule in Refs . [ 2 ] - [ 4 ] , where the Architectures for Real - Time LDPC Decoding

  • R. Joseph

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