A parallel ASIC VLSI neurocomputer for a large number of neurons and billion connections per second speed

  title={A parallel ASIC VLSI neurocomputer for a large number of neurons and billion connections per second speed},
  author={Y. Shimokawa and Yutaka Fuwa and Naruhiko Aramaki},
  journal={[Proceedings] 1991 IEEE International Joint Conference on Neural Networks},
  pages={2162-2167 vol.3}
  • Y. Shimokawa, Y. Fuwa, N. Aramaki
  • Published 18 November 1991
  • Computer Science
  • [Proceedings] 1991 IEEE International Joint Conference on Neural Networks
A programmable high-performance and high-speed neurocomputer for a large neural network is developed using an application specific IC (ASIC) neurocomputing chip made by CMOS VLSI technology. The neurocomputer consists of one master node and multiple slave nodes which are connected by two data paths, a broadcast bus and a ring bus. The neurocomputer was built on one printed circuit board having 50 VLSI chips that offers 1-2 billion connections/s. This computer uses SIMD (single-instruction… 
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