A novel states recovery technique for the TMR softcore processor

Abstract

The present paper describes a technique for ensuring re- liable softcore processor implementation on SRAM-based Field Programmable Gate Arrays (FPGAs), which can han- dle the effects of Single Event Upsets (SEUs). We pro- pose the Triple Modular Redundancy (TMR) scheme cou- pled with dynamic partial reconfiguration to remove SEUs from the configuration… (More)
DOI: 10.1109/FPL.2009.5272423

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