A novel soft error hardened latch design in 90nm CMOS

@article{Shirinzadeh2012ANS,
  title={A novel soft error hardened latch design in 90nm CMOS},
  author={Saeideh Shirinzadeh and Rahebeh Niaraki Asli},
  journal={The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)},
  year={2012},
  pages={60-63}
}
As a consequence of increasing density and decreasing supply voltage in modern VLSI circuits, gate capacitances and stored charge in sensitive nodes are considerably reduced. This has made sub-100nm CMOS circuits so vulnerable to radiation induced transient faults (TFs). This paper proposes a novel hardened latch design in 90nm CMOS technology. The proposed latch utilizes Schmitt trigger circuits and redundant feedback loops in order to mask transient pulses and harden internal nodes. A… CONTINUE READING

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