A novel self-calibration scheme for 12-bit 50MS/s SAR ADC

Abstract

This paper presents a low-power 12-bit 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using single input condition for Built-In Self Test (BIST) that uses a novel self-calibration scheme to reduce both offset voltage of a comparator and capacitor mismatch of the DAC. The proposed self-calibration scheme changes the offset… (More)

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