A novel self-aligned highly reliable sidewall split-gate flash memory

@article{Cho2006ANS,
  title={A novel self-aligned highly reliable sidewall split-gate flash memory},
  author={Caleb Yu-Sheng Cho and Ming-Jer Chen and Chiou-Feng Chen and P. Tuntasood and D.-T. Fan and Tseng-Yi Liu},
  journal={IEEE Transactions on Electron Devices},
  year={2006},
  volume={53},
  pages={465-473}
}
A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F/sup 2/ (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 10/sup 5/ confirm the novel… CONTINUE READING

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