A novel method in fractional synthesizers for a drastic decrease in lock time

@article{Ghasemzadeh2014ANM,
  title={A novel method in fractional synthesizers for a drastic decrease in lock time},
  author={Mehdi Ghasemzadeh and Amin Akbari and Neda Mohabbatian and Khayrollah Hadidi and Abdullah Khoei},
  journal={2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)},
  year={2014},
  pages={138-141}
}
A 1GHz frequency divider is presented in this paper. The proposed architecture aims to minimize lock time in Phase-Locked Loops (PLLs). Proposed structure has been simulated by HSPICE software in a typical 0.18μm CMOS technology at the supply voltage of 1.8V. Simulation results show that the designed divider locks in 2-20μs which is a lower lock time compared to conventional PLLs.