A novel high performance distributed arithmetic adaptive filter implementation on an FPGA

@article{Allred2004ANH,
  title={A novel high performance distributed arithmetic adaptive filter implementation on an FPGA},
  author={Daniel J. Allred and Heejong Yoo and Venkatesh Krishnan and Walter Huang and David V. Anderson},
  journal={2004 IEEE International Conference on Acoustics, Speech, and Signal Processing},
  year={2004},
  volume={5},
  pages={V-161}
}
In this paper, an FIR adaptive filter implementation, using a multiplier-free architecture, is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT… CONTINUE READING
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