A novel fault detection and correction technique for memory applications

Abstract

As a result of technology scaling and higher integration densities there may be variations in parameters and noise levels which will lead to larger error rates at various levels of the computations. As far as memory applications are concerned the soft errors and single event upsets are always a matter of problem. The paper mainly focuses on the design of an efficient Majority Logic Detector/Decoder (MLDD) for fault detection along with correction of fault for memory applications, by considerably reducing fault detection time. The error detection and correction method is done by one step majority logic decoding and is made effective for Euclidean Geometry Low Density Parity Check Codes (EG-LDPC). Even though majority decodable codes can correct large number of errors, they need high decoding time for detection of errors and ML Decoding method may take same fault detecting time for both erroneous and error free code words, which in turn delays the memory performance. The proposed fault-detection method can detect the fault in less decoding cycles (almost in three). When the data read is error free, it can obviously reduce memory access time. The technique keeps the area overhead minimal and power consumption low for large code word sizes.

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Cite this paper

@article{Jayarani2013ANF, title={A novel fault detection and correction technique for memory applications}, author={M. A. Jayarani and M. Jagadeeswari}, journal={2013 International Conference on Computer Communication and Informatics}, year={2013}, pages={1-6} }