A novel architecture for LZSS compression of configuration bitstreams within FPGA

Abstract

Partial run-time reconfigurability of current FPGAs has been shown to be beneficial in many application domains. However, utilization of this feature is limited by the time it takes to reconfigure a selected part of an FPGA. This is commonly addressed by compression of a configuration bitstream, often using LZSS algorithm. To allow speeding up the… (More)
DOI: 10.1109/DDECS.2017.7934587

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