A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

@article{Singh2010ANS,
  title={A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications},
  author={Jawar Singh and Krishnan Ramakrishnan and Saurabh Mookerjea and Suman Datta and Narayanan Vijaykrishnan and Dhiraj K. Pradhan},
  journal={2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)},
  year={2010},
  pages={181-186}
}
Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this limitation, 7T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6T SRAM design using Si… CONTINUE READING
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