A novel 5.46 mW H.264/AVC video stream parser IC

This paper presents a 5.46 mW H.264/AVC Video Stream Parser implemented in 65 nm. The differences between targeting a video stream parser architecture for a 65 nm CMOS ASIC and a Virtex 5 FPGA are also compared. Overall, the ASIC implementations showed higher performance and lower area than an FPGA, with a 60% increase in performance and 6x decrease in area… CONTINUE READING