A new structure of low-power and low-voltage double-edge triggered flip-flop

In this paper a novel low-power double-edge triggered flip-flop is introduced. Double-edge triggered Flip-Flops have the data signal changes on both the clock edges. Thus, low swing clock results in lower power consumption and the data throughout are preserved. Today, the leakage current has become a critical feature for integrated circuit (IC) designers… CONTINUE READING