A new low-power high-speed single-clock-cycle binary comparator

@article{Frustaci2010ANL,
  title={A new low-power high-speed single-clock-cycle binary comparator},
  author={Fabio Frustaci and Stefania Perri and Marco Lanuzza and Pasquale Corsonello},
  journal={Proceedings of 2010 IEEE International Symposium on Circuits and Systems},
  year={2010},
  pages={317-320}
}
This paper presents a new ultra-low power high-speed single-clock-cycle binary comparator. It is based on a novel parallel-prefix algorithm which drastically reduces the switching activity of the internal nodes of the circuit. When implemented by using the ST 90nm-1V technology, the proposed 64-bit comparator exhibits an energy dissipation of only 0.77μW/MHz and a delay of 258ps. With respect to a recently published low-power high-speed parallel-prefix adder, the proposed design shows an energy… CONTINUE READING