A new dynamic test vector compaction for automatic test pattern generation

@article{Ayari1994AND,
  title={A new dynamic test vector compaction for automatic test pattern generation},
  author={Bechir Ayari and Bozena Kaminska},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
  year={1994},
  volume={13},
  pages={353-358}
}
In this paper, a new approach for dynamic test vector compaction, for combinational logic circuits, called COMPACT, is proposed. A new data structure of test vectors permits easy verification of compactability between test vectors with minimal memory requirements. Experimental results obtained by adding the proposed algorithm to a simple PODEM program and applying it to the ISCAS-85 benchmark circuits are presented. The resulting test vector reduction is up to 40% for small circuits and around… CONTINUE READING
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