A new approach to minimize leakage power in nano-scale VLSI adder


Leakage power became very predominant for nano scale devices i.e 90nm and 45nm. ITRS reports that leakage power dissipation may come to dominate total power consumption [1]. We propose a novel approach, which reduces leakage current while saving exact logic state. We designed Four bit Adder using traditional sleep transistors plus two additional transistors… (More)
DOI: 10.1145/1741906.1742108

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