A new approach of presenting reversible logic gate in nanoscale


Conventional lithography-based VLSI design technology deployed to optimize low-powered-computing and higher scale integration of semiconductor components. However, this downscaling trend confronts serious challenges of tunneling and leakage current increment to the Complementary Metal-Oxide-Semiconductor (CMOS) technology on nanoscale regimes. To resolve… (More)
DOI: 10.1186/s40064-015-0928-4


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