A new RSA cryptosystem hardware design based on Montgomery's algorithm

@article{Yang1998ANR,
  title={A new RSA cryptosystem hardware design based on Montgomery's algorithm},
  author={Ching-Chao Yang and Tian-Sheuan Chang and C. W. Jen},
  journal={IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing},
  year={1998},
  volume={45},
  pages={908-913}
}
In this paper, we propose a new algorithm based on Montgomery's algorithm to calculate modular multiplication that is the core arithmetic operation in an RSA cryptosystem. The modified algorithm eliminates over large residue and has very short critical path delay that yields a very high speed processing. The new architecture based on this modified algorithm takes about 1.5n/sup 2/ clock cycles on the average to finish one n-bit RSA operation. We have implemented a 512-bit single-chip RSA… 
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A bit-level systolic array for RSA public key cryptosystem is designed based on the modified Montgomery's algorithm, which leads to both simpler architecture and better performance.
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