A new LDPC decoder hardware implementation with improved error rates

@article{Schlafer2015ANL,
  title={A new LDPC decoder hardware implementation with improved error rates},
  author={P. Schlafer and Stephanie Scholl and Emanuele Leonardi and Norbert Wehn},
  journal={2015 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT)},
  year={2015},
  pages={1-6}
}
LDPC codes are commonly decoded by conventional belief propagation algorithms like the min-sum algorithm. However especially for small block lengths belief propagation performs poorly in comparison to maximum likelihood decoding. In this paper we propose a new decoding algorithm, that is inspired by augmented belief propagation from literature and present hardware architectures and implementations for 28nm ASIC technology. The new decoder has a much higher complexity, but provides a gain of up… CONTINUE READING

Citations

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Saturated min-sum decoding: An “afterburner” for LDPC decoder hardware

  • 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Advanced iterative channel coding schemes: When Shannon meets Moore

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