A new ATPG method for efficient capture power reduction during scan testing

@article{Wen2006ANA,
  title={A new ATPG method for efficient capture power reduction during scan testing},
  author={Xiaoqing Wen and Seiji Kajihara and Kohei Miyase and Tatsuya Suzuki and Kewal K. Saluja and Laung-Terng Wang and Khader S. Abdel-Hafez and Kozo Kinoshita},
  journal={24th IEEE VLSI Test Symposium},
  year={2006},
  pages={6 pp.-65}
}
High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive JR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling… CONTINUE READING
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