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A multilevel hierarchical interconnection structure for FPGA


Creation of large FPGAs needs radical efficient changes in architecture to improve speed, density and software mapping time. Based on industry experience with standard ASICs, we believe that partitioning and hierarchy become an obligation for FPGA hardware and software developments. As an alternative we propose a new Multilevel hierarchical FPGA (MFPGA) architecture where logic blocks and routing resources are sparsely partitioned into multilevel clustered structure. Since the routing resources consume most of the FPGA area, we focus on interconnect check. We try to achieve the best area efficiency by balancing interconnect and logic block utilization. The proposed MFPGA interconnect unifies two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology, and an upward network that uses hierarchy. The Downward network uses linear populated and unidirectional switch boxes and gives one path from each wire-source in the top to each leaf (logic block) in the lowest level. The upward network connects the logic blocks outputs and the input pads to the different levels of the downward network. Studies based on the Rent's Rule show that wiring and switch requirements in the MFPGA grow slower than in traditional topologies. We used MCNC benchmark circuits to compare the switch and area requirements between our MFPGA architecture and the traditional mesh topology. New software tools for placement and routing were developed to conduct this study on the MFPGA architecture. Expermimental results show that MFPGA can implement circuits with fewer switches and a smaller total area than mesh architecture.

DOI: 10.1145/1117201.1117239