A multi-level DRAM with fast read and low power consumption

@article{Liu2005AMD,
  title={A multi-level DRAM with fast read and low power consumption},
  author={Bo Liu and J. F. Frenzel and R. Wells},
  journal={2005 IEEE Workshop on Microelectronics and Electron Devices, 2005. WMED '05.},
  year={2005},
  pages={59-62}
}
In this paper, we present a new, multi-level DRAM design, which can store 3 voltage levels (0, Vcc, and Vcc/2) in a single memory cell. This multi-level DRAM requires no special reference voltage and simplifies design of the peripheral circuits. Coding algorithms may be used to provide binary data immediately after first read, with the second read operation… CONTINUE READING