A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores

Abstract

Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahertz speeds. However, such a tremendous computational capability comes at a high price in terms of power consumption and design effort in distributing a global clock signal across… (More)
DOI: 10.1145/871506.871600

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